The present invention is directed to multi-station data processing systems, and more particularly to systems wherein multiple intelligent terminals share a large common memory.
In multi-processor systems employing a large common memory, a single sequential-type controller is typically used, such as a high speed 370 (e.g., a 3081) processor. The shared common memory may, e.g., include a primary memory (typically a random access memory) and a backing store (e.g., a disc). When a request for data is received, the processor must search the contents of the primary memory to determine if the requested record has been stored and, if not, request a data transfer from the backing store to the primary memory. When a plurality of data requests are received from different terminals, the sequential controller must process each request in sequence, and the system must therefore either use a very high speed processor, resulting in substantial cost increase, or use a less expensive and lower speed processor, resulting in unsatisfactory delays in memory access.
There is a need, then, for a memory control system which is both efficient and inexpensive.